• Implemented 32-bit 5 stage pipelined RISC-V processor supporting the RV32IMF ISA which comprises of Integer Arithmetic, Multiplication/Division and Floating-Point Arithmetic.
• Designed Five Pipeline Stages included Instruction Fetch, Decode, Execute, Memory, Write Back along with Forwarding and Stalling Units for handling Data Hazards.
• Technologies: Verilog HDL, Xilinx ISE. Hardware Used: Xilinx Zedboard Zync 7000 SoC.